In microprocessor design, the controller commands the design is a very critical part of [124], its structure and the processor can directly determine the performance and design complexity and cost of the RISC processor in the use of the Decoding hard wiring and controllers, the design of its controller on the more crucial. To improve the efficiency of the implementation of the directive and the implementation of speed machines, processors generally use the pipeline design technology. The current general use microprocessor 3 to 5 lines (also adopted seven lines), its shortcomings, when more than three lines, a high degree of complexity of design, data related to the conflict and transfer the handling of the conflict to use up a lot of design resources, Some are not suitable for application in the low cost of microprocessor design.In the smart I / O data-processing SoC designs, the need for a middle-handling capacity of 16 MCU, the existing processors can not be cost-effective IP better meet the requirements and therefore decided to develop a 16 MHz frequency When handling capacity can reach 8 MIPS of 16 I / O-channel processor (hereinafter referred to as IPU16).The design strategy is to meet the performance requirements under the premise of as much as possible to simplify design, reduce the final area of chip design and power consumption. In order combination of technology and control lines control the advantage of technology, in IPU16 in the design and realization of a simple logic, higher performance, better-performing pseudo-four flow controller structure, is the core of the implementation of the directive Is a four-phase state, the use of two lines to achieve the implementation of the four water directives.
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