主机与从机英语

The host computerupper computer superior machine 上位机inferior machinelower computer下位机中位机我没听过我不知道LZ说的是那方面的电子行业，我写的是关于计算机方面的上位机和下位机也可以[C和PLC

主机[动力]mainengine；[计]mainframe更多释义>>[网络短语]主机Host;Hostcomputer;mainframe主机租用Dedicatedhosting;Dedicatedserver;SEO主机功率WeightofMainEngine;MainPower;KW

瀑布汗这么多给200分有人干

(1) single-chip 3 to the way communications, a data section 9 for the "1" on behalf of the address frame, in order to "0" on behalf of the data frame. (2) to set the communication baud rate is 1200bps. (3) 00H is the address of a frame sent from the machine work on all of the control order, order the resumption of the slave SM2 = 1, waiting to receive state. (4) and from the host machine for the contact process; Host Address frame issued by the call from the machine frame to host the return address in order to determine the host machine from a contact. Host control commands issued from the machine in accordance with an order or to receive the host data blocks or data blocks sent to the host. (5) control the host sending the command code as follows: AAH: set table base; BBH: the number of read table; CCH: open table settings; DDH: clearance table settings EEH: Checksum error; EDH: at the end of transmission. (6) the composition of the format of data blocks: one block for the final at the end of EDH, until at the end of the contents of the data blocks can be frame opcode, address, code frames and data frames. In order to achieve multi-machine communications, all firing circuits and all the oscillation frequency of the oscillation frequency receiver circuit must be adjusted in line, in order to ensure the normal communications, to prevent their own fat, then the direction of data transmission must be half-duplex transmission, transceiver in the launch must be shielded to receive its own interrupt, interrupted open after the end of the launch. Multi-machine communication process as follows: (1) all from the machine SM2 = 1, at the address to receive the status of frame. (2) a host address information, which includes 8-bit address, the first 9 to "1", with the required contact from the machine. (3) from the machine after the address information received, each with its own compared to the address; in line for the address from the machine so that RI = 0, TB8 = 1, to send its own address, and SM2 = 0, TI = 1, to wait for the receiving host then sent all the information; the address does not match the slave remained SM2 = 1 state, then sent to the host of the data sent up to take no notice of a new address information. (4) to address the host will receive SCON 9th TB8-ching "0", and then proceed to address proof, address proof, if passed, from the machine has been contacted, send control commands to the communications signal; address error proofing on there is no contact from the machine, send the end of the communication command, modify SCON 9th, TB8 home will be "1." Addressing the host to be sent from the machine control commands and data, a data section 9 for the "0", that send data or control commands. 5) called from the plane after receiving a command to the command analysis information collected at the scene to carry out certain data processing, in accordance with the requirements of the host to return data and the implementation of the host orders. If an order to end the communication, then immediately buy SM2 = 1, the end of this communication, to wait for the next communication, otherwise the implementation of appropriate action, for an order to return information, home TB8 = 0, return the correct information in response to post-SM2 = 1, to resume its only state to receive the address data frame. (6) host receiving orders to return to the end of communication message SCON modify the first nine, will be home TB8 "1", ready for the next round of communications. 2. Hardware Mainly include the infrared transmitter and infrared receiver circuit of two parts: Infrared transmitter Data transmission in the infrared signal modulation methods, the use of pulse modulation of the binary code is not zero. This modulation is simpler, more convenient all codec will help simplify the circuit. Infrared emission circuit as shown in Figure 2. 455KHZ the crystal by CRY, inverter 74HC04 and resistors, capacitors consisting of the square wave oscillator signal generated 455KHZ. By the pulse divider 74LS92, six of the pulse frequency as a signal 75.83KHZ. Another D flip-flop consisting of 2-/ 38KHZ shaping circuit into a square wave signal. By the single-chip asynchronous serial port TX of the serial data output signal to the NAND gate input of the 74HC00. Doors with non-38KHZ another input termination of the carrier signal. And non-gate transistor used to control the output signal of the open or off to control the launch tube infrared send a message. This achieved by the serial port TX of the serial data output directly modulated carrier signal to carry out the purpose of infrared data transmission. Transmitter modulation system using time division modulation keying rate. After the reduction due to single-chip, TXD pin is high, in order to meet the requirements of synchronous, use of low-level synchronization pulse, with the non-gate (U3) become high after the synchronization pulse. Therefore, single-chip encoder TXD should be sent by the anti-code.你要的是这样吗